View ADCLK846_4607688.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer ADCLK846
FEATURES
Selectable LVDS/CMOS outputs Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs <16 mW per channel (100 MHz operation) 54 fs integrated jitter (12 kHz to 20 MHz) 100 fs additive broadband jitter 2.0 ns propagation delay (LVDS) 135 ps output rise/fall (LVDS) 65 ps output-to-output skew (LVDS) Sleep mode Pin-programmable control 1.8 V power supply
FUNCTIONAL BLOCK DIAGRAM
ADCLK846
LVDS/CMOS OUT0 (OUT0A) OUT0 (OUT0B) VREF OUT1 (OUT1A) CLK CLK CTRL_A LVDS/CMOS OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) OUT3 (OUT3B) OUT4 (OUT4A) CTRL_B SLEEP OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B)
07226-001
OUT1 (OUT1B)
APPLICATIONS
Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation
Figure 1.
GENERAL DESCRIPTION
The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout buffer optimized for low jitter and low power operation. Possible configurations range from 6 LVDS to 12 CMOS outputs, including combinations of LVDS and CMOS outputs. Two control lines are used to determine whether fixed blocks of outputs are LVDS or CMOS outputs. The clock input accepts various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection. The SLEEP pin enables a sleep mode to power down the device. This device is available in a 24-pin LFCSP package. It is specified for operation over the standard industrial temperature range of -40C to +85C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
ADCLK846 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics ............................................................. 3 Timing Characteristics ................................................................ 4 Clock Characteristics ................................................................... 5 Logic and Power Characteristics ................................................ 5 Absolute Maximum Ratings............................................................ 6 Determining Junction Temperature .......................................... 6 ESD Caution .................................................................................. 6 Thermal Performance .................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ..............................................8 Functional Description .................................................................. 11 Clock Inputs ................................................................................ 11 AC-Coupled Applications ......................................................... 11 Clock Outputs ............................................................................. 12 Control and Function Pins........................................................ 12 Power Supply............................................................................... 12 Applications Information .............................................................. 13 Using the ADCLK846 Outputs for ADC Clock Applications ................................................................................ 13 LVDS Clock Distribution .......................................................... 13 CMOS Clock Distribution ........................................................ 13 Input Termination Options ....................................................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
6/09--Rev. 0 to Rev. A No Content Updates ...................................................... Throughout 4/09--Revision 0: Initial Version
Rev. A | Page 2 of 16
ADCLK846 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical values are given for VS = 1.8 V and TA = 25C, unless otherwise noted. Minimum and maximum values are given over the full VS = 1.8 V 5% and TA = -40C to +85C variations, unless otherwise noted. Input slew rate > 1 V/ns, unless otherwise noted. Table 1.
Parameter CLOCK INPUTS Input Frequency Input Sensitivity, Differential Input Level Input Common-Mode Voltage Input Common-Mode Range Input Voltage Offset Input Sensitivity, Single-Ended Input Resistance (Differential) Input Capacitance Input Bias Current (Each Pin) LVDS CLOCK OUTPUTS Output Frequency Differential Output Voltage Offset Voltage Short-Circuit Current CMOS CLOCK OUTPUTS Output Frequency Output Voltage High Output Voltage Low Reference Voltage Output Voltage Output Resistance Output Current VOH VOL VREF VS/2 - 0.1 VS/2 60 VS/2 + 0.1 500 V A 500 A VS - 0.1 VS - 0.35 0.1 0.35 250 MHz V V V V VCM VCMR VS/2 - 0.1 0.4 30 150 7 2 -350 +350 Symbol Min 0 150 1.8 VS/2 + 0.05 VS - 0.4 Typ Max 1200 Unit MHz mV p-p V p-p V V mV mV p-p k pF A Conditions Differential input Jitter performance is improved with higher slew rates (greater voltage swing) Larger voltage swings can turn on the protection diodes and can degrade jitter performance Inputs are self-biased; enables ac coupling Inputs are dc-coupled with 200 mV p-p signal applied CLK ac-coupled; CLK ac-bypassed to ground
CIN
Full input swing Termination = 100 ; differential (OUTx, OUTx) See Figure 9 for a swing vs. frequency plot
VOD VOD VOS VOS ISA, ISB
247 1.125
344 1.25 3
1200 454 50 1.375 50 6
MHz mV mV V mV mA
Each pin (output shorted to GND ) Single-ended; termination = open OUTx and OUTx in phase With 10 pF load each output; see Figure 16 for swing vs. frequency At 1 mA load At 10 mA load At 1 mA load At 10 mA load
Rev. A | Page 3 of 16
ADCLK846
TIMING CHARACTERISTICS
Table 2.
Parameter LVDS OUTPUTS Output Rise/Fall Time Propagation Delay, CLK-to-LVDS Output Temperature Coefficient Output Skew 1 All LVDS Outputs on the Same Part All LVDS Outputs Across Multiple Parts Additive Time Jitter Integrated Random Jitter Symbol tR, tF tPD Min Typ 135 2.0 2.0 Max 235 2.7 Unit ps ns ps/C ps ps fs rms fs rms fs rms fs rms fs rms BW = 12 kHz to 20 MHz, CLK = 1000 MHz BW = 50 kHz to 80 MHz, CLK = 1000 MHz BW = 12 kHz to 20 MHz, CLK = 1000 MHz Input slew rate = 1 V/ns Calculated from spur energy with an interferer 10 MHz offset from carrier Termination = open 20% to 80%; CMOS load = 10 pF 10 pF load Conditions Termination = 100 differential; 3.5 mA 20% to 80% measured differentially VICM = VREF, VID = 0.5 V
1.5
65 390 54 74 86 150 260
Broadband Random Jitter 2 Crosstalk-Induced Jitter CMOS OUTPUTS Output Rise/Fall Time Propagation Delay, CLK-to-CMOS Output Temperature Coefficient Output Skew2 All CMOS Outputs on the Same Part All CMOS Outputs Across Multiple Parts Additive Time Jitter Integrated Random Jitter Broadband Random Jitter 3 Crosstalk-Induced Jitter LVDS-TO-CMOS OUTPUT SKEW2 LVDS Output(s) and CMOS Output(s) on the Same Part
1 2 3
tR, tF tPD
2.5
525 3.2 2.2
950 4.2
ps ns ps/C ps ps fs rms fs rms fs rms
175 640 56 100 260
BW = 12 kHz to 20 MHz, CLK = 200 MHz Input slew = 2 V/ns; see Figure 11 Calculated from spur energy with an interferer 10 MHz offset from carrier CMOS load = 10 pF and LVDS load = 100
0.8
1.6
ns
This is the difference between any two similar delay paths while operating at the same voltage and temperature. Measured at rising edge of clock signal. Calculated from SNR of ADC method.
Rev. A | Page 4 of 16
ADCLK846
CLOCK CHARACTERISTICS
Table 3. Clock Output Phase Noise
Parameter CLK-TO-LVDS ABSOLUTE PHASE NOISE 1000 MHz Min Typ -90 -108 -117 -126 -134 -141 -146 -100 -117 -128 -138 -147 -153 -156 Max Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Conditions Input slew rate > 1 V/ns At 10 Hz offset At 100 Hz offset At 1 kHz offset At 10 kHz offset At 100 kHz offset At 1 MHz offset At 10 MHz offset Input slew rate > 1 V/ns At 10 Hz offset At 100 Hz offset At 1 kHz offset At 10 kHz offset At 100 kHz offset At 1 MHz offset At 10 MHz offset
CLK-TO-CMOS ABSOLUTE PHASE NOISE 200 MHz
LOGIC AND POWER CHARACTERISTICS
Table 4. Control Pin Characteristics
Parameter CONTROL PINS (CTRL_A, CTRL_B, SLEEP) 1 Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance POWER Supply Voltage Requirement LVDS Outputs, Full Operation LVDS at 100 MHz LVDS at 1200 MHz CMOS Outputs, Full Operation CMOS at 100 MHz CMOS at 250 MHz Sleep Power Supply Rejection 2 LVDS CMOS
1 2
Symbol
Min
Typ
Max
Unit
Conditions
VIH VIL IIH IIL
VS - 0.4 5 -5 8 2 0.4 20 +5
V V A A pF V mA mA mA mA mA VS = 1.8 V 5% All outputs enabled as LVDS and loaded, RL = 100 All outputs enabled as LVDS and loaded, RL = 100 All outputs enabled as CMOS and loaded, CMOS load = 10 pF All outputs enabled as CMOS and loaded, CMOS load = 10 pF SLEEP pin pulled high; does not include power dissipated in external resistors
VS
1.71
1.8 55 110 75 155
1.89 70 130 95 190 3
PSRTPD PSRTPD
0.9 1.2
ps/mV ps/mV
These pins each have a 200 k internal pull-down resistor.
Change in TPD per change in VS.
Rev. A | Page 5 of 16
ADCLK846 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Supply Voltage VS to GND Inputs CLK and CLK CMOS Inputs Outputs Maximum Voltage Voltage Reference Voltage (VREF) Operating Temperature Range Ambient Junction Storage Temperature Range Rating 2V -0.3 V to +2 V -0.3 V to +2 V -0.3 V to +2 V -0.3 V to +2 V -40C to +85C 150C -65C to +150C
DETERMINING JUNCTION TEMPERATURE
To determine the junction temperature on the application PCB, use the following formula: TJ = TCASE + (JT x PD) where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the customer at top center of the package. JT is indicated in Table 6. PD is the power dissipation. Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approximation of TJ by the equation TJ = TA + (JA x PD) where TA is the ambient temperature (C). Values of JB are provided for package comparison and PCB design considerations.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
THERMAL PERFORMANCE
Table 6.
Parameter Junction-to-Ambient Thermal Resistance Still Air 0.0 m/sec Airflow Moving Air 1.0 m/sec Airflow 2.5 m/sec Airflow Junction-to-Board Thermal Resistance Moving Air 1.0 m/sec Airflow Junction-to-Case Thermal Resistance Moving Air Die-to-Heat Sink Junction-to-Top-of-Package Characterization Parameter Still Air 0 m/sec Airflow
1
Symbol JA
Description Per JEDEC JESD51-2
Value 1
Unit
57.0 JMA Per JEDEC JESD51-6 49.8 44.7 JB Per JEDEC JESD51-8 35.2 JC Per MIL-STD 883, Method 1012.1 2.0 JT Per JEDEC JESD51-2 1.0
C/W C/W C/W
C/W
C/W
C/W
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations.
Rev. A | Page 6 of 16
ADCLK846 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
OUT0 (OUT0A) OUT0 (OUT0B) VS OUT1 (OUT1A) OUT1 (OUT1B) VS
VREF CLK CLK VS CTRL_A CTRL_B
1 2 3 4 5 6
24 23 22 21 20 19
PIN 1 INDICATOR
ADCLK846
TOP VIEW (Not to Scale)
18 17 16 15 14 13
OUT2 (OUT2A) OUT2 (OUT2B) VS OUT3 (OUT3A) OUT3 (OUT3B) VS
SLEEP 7 OUT5 (OUT5B) 8 OUT5 (OUT5A) 9 VS 10 OUT4 (OUT4B) 11 OUT4 (OUT4A) 12
NOTES: 1. EXPOSED PADDLE MUST BE CONNECTED TO GND.
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 1 2 3 4, 10, 13, 16, 19, 22 5 6 7 8 9 11 12 14 15 17 18 20 21 23 24 (25) Mnemonic VREF CLK CLK VS CTRL_A CTRL_B SLEEP OUT5 (OUT5B) OUT5 (OUT5A) OUT4 (OUT4B) OUT4 (OUT4A) OUT3 (OUT3B) OUT3 (OUT3A) OUT2 (OUT2B) OUT2 (OUT2A) OUT1 (OUT1B) OUT1 (OUT1A) OUT0 (OUT0B) OUT0 (OUT0A) EPAD Description Reference Voltage. Clock Input (Negative). Clock Input (Positive). Supply Voltage. CMOS Input Control for Output 1 to Output 0. (0: LVDS, 1: CMOS.) CMOS Input Control for Output 5 to Output 2. (0: LVDS, 1: CMOS.) CMOS Input for Sleep Mode. (0: normal operation, 1: sleep.) Complementary Side of Differential LVDS Output 5, or CMOS Output 5 on Channel B. True Side of Differential LVDS Output 5, or CMOS Output 5 on Channel A. Complementary Side of Differential LVDS Output 4, or CMOS Output 4 on Channel B. True Side of Differential LVDS Output 4, or CMOS Output 4 on Channel A. Complementary Side of Differential LVDS Output 3, or CMOS Output 3 on Channel B. True Side of Differential LVDS Output 3, or CMOS Output 3 on Channel A. Complementary Side of Differential LVDS Output 2, or CMOS Output 2 on Channel B. True Side of Differential LVDS Output 2, or CMOS Output 2 on Channel A. Complementary Side of Differential LVDS Output 1, or CMOS Output 1 on Channel B. True Side of Differential LVDS Output 1, or CMOS Output 1 on Channel A. Complementary Side of Differential LVDS Output 0, or CMOS Output 0 on Channel B. True Side of Differential LVDS Output 0, or CMOS Output 0 on Channel A. Exposed Paddle. The exposed paddle must be connected to ground.
Rev. A | Page 7 of 16
07226-002
ADCLK846 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 1.8 V, TA = 25C, unless otherwise noted.
2
2
07226-003
CH2 100mV
M 200ps 10.0GS/s
CH1
-36.0mV
CH2 100mV
M 1.0ns 10.0GS/s
CH1
-36.0mV
Figure 3. LVDS Output Waveform at 1200 MHz
Figure 6. LVDS Output Waveform at 200 MHz
2.3
2.4 2.3
2.2
PROPAGATION DELAY (ns)
PROPATATION DELAY (ns)
2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5
2.1
2.0
1.9
1.8
07226-004
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
400
600
800
1000
1200
1400
1600
INPUT DIFFERENTIAL (V p-p)
INPUT COMMON-MODE (mV)
Figure 4. LVDS Propagation Delay vs. VID
Figure 7. LVDS Propagation Delay vs. VCM
55
DIFFERENTIAL OUTPUT SWING (mV p-p)
715
54 53 52
DUTY CYCLE (%)
705
51 50 49 48 47 46
07226-105
695
685
0
200
400
600
800
1000
1200
1.72
1.82 POWER SUPPLY (V)
1.92
FREQUENCY (MHz)
Figure 5. LVDS Output Duty Cycle vs. Frequency
Figure 8. LVDS Output Swing vs. Power Supply Voltage
Rev. A | Page 8 of 16
07226-014
45
675 1.62
07226-007
1.7 0.1
1.4 200
07226-006
ADCLK846
900 DIFFERENTIAL OUTPUT SWING (mV p-p)
-80 -90
800
-100
PHASE NOISE (dBc/Hz)
ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672), WENZEL 5x MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A WENZEL 2x MULTIPLIER (P/N LNDD-500-14-14-1-D).
-110 -120 -130 -140 -150 -160 -170 CLOCK SOURCE ADCLK846
700
600
500
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
400
07226-009
100
1k
10k
100k
1M
10M
100M
INPUT FREQUENCY (MHz)
FREQUENCY OFFSET (Hz)
Figure 9. LVDS Differential Output Swing vs. Input Frequency
Figure 12. Absolute Phase Noise LVDS at 1000 MHz
150
200
125 150
CURRENT (mA)
BOTH BANKS CMOS BANK A CMOS, BANK B LVDS
75
CURRENT (mA)
100
100
50
50 25 BANK A LVDS, BANK B CMOS 0 25 BOTH BANKS LVDS
07226-110
0
200
400
600
800
1000
1200
1400
1600
1800
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. LVDS Current vs. Frequency, All Banks Set to LVDS
Figure 13. LVDS/CMOS Current vs. Frequency with Various Logic Combinations
55 54 53 52
DUTY CYCLE (%)
500 450 400 350
JITTER (fS rms)
300 250 200 150 100 50
07226-011
51 50 49 48 47 46 0 50 100 150 200 250
07226-114
0
45
0
0.5
1.0
1.5
2.0
2.5
INPUT SLEW RATE (V/ns)
FREQUENCY (MHz)
Figure 11. Additive Broadband Jitter vs. Input Slew Rate
Figure 14. CMOS Output Duty Cycle vs. Frequency, 10 pF Load
Rev. A | Page 9 of 16
07226-113
0
07226-112
-180 10
ADCLK846
1
07226-115
1
07226-018
CH1 300mV
1.25ns/DIV
CH1
954mV
CH1 300mV
5.0ns/DIV
CH1
954mV
Figure 15. CMOS Output Waveform at 200 MHz, 10 pF Load
Figure 18. CMOS Output Waveform at 50 MHz, 10 pF Load
1.9 1.8 1.7
OUTPUT SWING (V)
1.8 RL = 750 25C
OUTPUT SWING (V)
RL = 1k
1.7
1.6 85C 1.5 1.4 1.3 1.2 1.1 50
1.6 RL = 500 RL = 300 1.5
07226-116
100
150 FREQUENCY (MHz)
200
250
0
50
100
150
200
250
FREQUENCY (MHz)
Figure 16. CMOS Output Swing vs. Frequency and Temperature, 10 pF Load
Figure 19. CMOS Output Swing vs. Frequency and Resistive Load
2.0 1.9 1.8
OUTPUT SWING (V)
CL = 5pF
1.7 1.6 1.5 1.4 1.3 1.2 1.1 0 50 100
CL = 10pF
CL = 20pF
150
200
250
FREQUENCY (MHz)
Figure 17. CMOS Output Swing vs. Frequency and Capacitive Load
07226-017
1.0
Rev. A | Page 10 of 16
07226-015
1.4
ADCLK846 FUNCTIONAL DESCRIPTION
The ADCLK846 clock input is distributed to all output channels. Each channel bank is pin programmable for either LVDS or CMOS levels. This allows the selection of multiple logic configurations ranging from 6 LVDS to 12 CMOS outputs, along with other combinations using both types of logic.
VS 9k CLK 9k 9.5k CLK 8.5k GND
07226-023
CLOCK INPUTS
The differential inputs of the ADCLK846 are internally selfbiased. The clock inputs have a resistor divider, which sets the common-mode level for the inputs. The complementary inputs are biased about 30 mV lower than the true input to avoid oscillations if the input signal ceases. See Figure 20 for the equivalent input circuit. The inputs can be ac-coupled or dc-coupled. Table 8 displays a guide for input logic compatibility. If a single-ended input is desired, this can be accommodated by ac or dc coupling to one side of the differential input. Bypass the other input to ground by a capacitor. Note that jitter performance degrades with low input slew rate, as shown in Figure 11. See Figure 28 through Figure 32 for different termination schemes.
Figure 20. ADCLK846 Input Stage
AC-COUPLED APPLICATIONS
When ac coupling is desired, the ADCLK846 offers two options. The first option requires no external components (excluding the dc blocking capacitor); it allows the user to couple the reference signal onto the clock input pins (see Figure 31). The second option allows the use of the VREF pin to set the dc bias level for the ADCLK846. The VREF pin can be connected to CLK and CLK through resistors. This method allows lower impedance termination of signals at the ADCLK846 (see Figure 32). The internal bias resistors are still in parallel with the external biasing. However, the relatively high impedance of the internal resistors allows the external termination to VREF to dominate. This is also useful if it is not desirable to offset the inputs slightly as previously mentioned using only the internal biasing.
Table 8. Input Logic Compatibility
Supply (V) 3.3 2.5 1.8 3.3 2.5 1.8 1.5 3.3 2.5 1.8 Logic CML CML CML CMOS CMOS CMOS HSTL LVDS LVPECL LVPECL LVPECL Common Mode (V) 2.9 2.1 1.4 1.65 1.25 0.9 0.75 1.25 2.0 1.2 0.5 Output Swing (V) 0.8 0.8 0.8 3.3 2.5 1.8 0.75 0.4 0.8 0.8 0.8 AC-Coupled Yes Yes Yes Not allowed Not allowed Yes Yes Yes Yes Yes Yes DC-Coupled Not allowed Not allowed Yes Not allowed Not allowed Yes Yes Yes Not allowed Yes Yes
Rev. A | Page 11 of 16
ADCLK846
CLOCK OUTPUTS
Each driver consists of a differential LVDS output or two singleended CMOS outputs (always in phase). When the LVDS driver is enabled, the corresponding CMOS driver is in tristate. When the CMOS driver is enabled, the corresponding LVDS driver is powered down and tristated. Figure 21 and Figure 22 display the equivalent output stage.
VS 3.5mA
POWER SUPPLY
The ADCLK846 requires a 1.8 V 5% power supply for VS. Best practice recommends bypassing the power supply on the PCB with adequate capacitance (>10 F) and bypassing all power pins with adequate capacitance (0.1 F) as close to the part as possible. The layout of the ADCLK846 evaluation board (ADCLK846/PCBZ) provides a good layout example.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK846 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The ADCLK846 dissipates heat through its exposed paddle. The PCB acts as a heat sink for the ADCLK846. The PCB attachment must provide a good thermal path to a larger heat dissipation area, such as the ground plane on the PCB. This requires a grid of vias from the top layer down to the ground plane. See Figure 23 for an example.
OUTx OUTx
3.5mA
Figure 21. LVDS Output Simplified Equivalent Circuit
VS
VS
OUTxA
07226-024
OUTxB
07226-025
VIAS TO GND PLANE
Figure 22. CMOS Equivalent Output Circuit
07226-026
CONTROL AND FUNCTION PINS
Logic Select for CTRL_A
CTRL_A selects either CMOS (high) or LVDS (low) logic for Output 1 and Output 0. This pin has an internal 200 k pulldown resistor.
Figure 23. PCB Land Example for Attaching Exposed Paddle
Logic Select for CTRL_B
CTRL_B selects either CMOS (high) or LVDS (low) logic for Output 5, Output 4, Output 3, and Output 2. This pin has an internal 200 k pull-down resistor.
Sleep Mode
SLEEP powers down the chip except for the band gap. The input is active high, which puts the outputs into a high-Z state. This pin has a 200 k pull-down resistor. The control pins are operational during sleep mode.
Rev. A | Page 12 of 16
ADCLK846 APPLICATIONS INFORMATION
USING THE ADCLK846 OUTPUTS FOR ADC CLOCK APPLICATIONS
Any high speed analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the ADC output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at 14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed approximately by
LVDS CLOCK DISTRIBUTION
The ADCLK846 provides clock outputs that are selectable as either CMOS or LVDS level outputs. LVDS is a differential output option that uses a current-mode output stage. The nominal current is 3.5 mA, which yields 350 mV output swing across a 100 resistor. The LVDS output meets or exceeds all ANSI/TIA/EIA-644 specifications. A recommended termination circuit for the LVDS outputs is shown in Figure 25. If ac coupling is necessary, place decoupling capacitors either before or after the 100 termination resistor.
VS VS
LVDS
100 100 DIFFERENTIAL (COUPLED)
LVDS
07226-028
1 SNR = 20log 2f ATJ

Figure 25. LVDS Output Termination
where: fA is the highest analog frequency being digitized. TJ is the rms jitter on the sampling clock. Figure 24 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB). See AN-756 Application Note and AN-501 Application Note for more information.
110 100 90 80
SNR (dB)
See the AN-586 Application Note at www.analog.com for more information on LVDS.
CMOS CLOCK DISTRIBUTION
The output drivers of the ADCLK846 can also be configured as CMOS drivers. When selected as a CMOS driver, each output becomes a pair of CMOS outputs. These outputs are 1.8 V CMOS compatible. When single-ended CMOS clocking is used, some of the following guidelines outlined in this section apply. Design point-to-point connections such that each driver has only one receiver, if possible. Connecting outputs in this manner allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the output trace. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the resistor is dependent on the board design and timing requirements (typically 10 to 100 is used). CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and signal integrity.
07226-076
1 SNR = 20log 2f T AJ
18 16
TJ = 100 fS 200 f 400 f 1ps 2ps
S S
14 12 10 8 6
07226-027
70 60 50 40 30 10
10p s
100
1k
fA FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)
Figure 24. SNR and ENOB vs. Analog Input Frequency
ENOB
Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sample clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment. The ADCLK846 features LVDS outputs that provide differential clock outputs, which enable clock solutions that maximize converter SNR performance. Consider the input requirements of the ADC (differential or single-ended, logic level, termination) when selecting the best clocking/converter solution.
Rev. A | Page 13 of 16
CMOS
10
60.4 (1.0 INCH) CMOS MICROSTRIP
Figure 26. Series Termination of CMOS Output
ADCLK846
Termination at the far end of the PCB trace is a second option. The CMOS outputs of the ADCLK846 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 27. Match the far-end termination network to the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.
VS 10 50 100 CMOS 100
07226-077
VCC
CLK CLK VCC
CLK CLK
07226-129
CMOS
Figure 29. Typical AC-Coupled or DC-Coupled CML Configurations (see Table 8 for CML Coupling Limitations)
Figure 27. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The ADCLK846 offers LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
CLK CLK 50 50
VCC - 2V
INPUT TERMINATION OPTIONS
For single-ended operation, always bypass unused input to GND as shown in Figure 31. Figure 32 illustrates the use of the VREF to provide low impedance termination into VS/2. In addition, Figure 32 shows a way to negate the 30 mV input offset with external resistor values. For example, use 1.8 V CMOS with long traces to provide farend termination.
CLK 100 CLK
CLK CLK 50 50
07226-130
VCC - 2V
Figure 30. Typical AC-Coupled or DC-Coupled LVPECL Configurations (see Table 8 for LVPECL DC Coupling Limitations)
CLK CLK
CLK CLK
CLK
07226-128
CLK
100
Figure 28. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configurations (see Table 8)
Figure 31. Typical 1.8 V CMOS Configurations for Short Trace Lengths (see Table 8 for CMOS compatibility)
VREF CLK CLK
07226-132
Figure 32. Use of the VREF to Provide Low Impedance Termination into VS/2
Rev. A | Page 14 of 16
07226-131
CLK
CLK
ADCLK846 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX 0.60 MAX 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP
19 18 EXPOSED PAD 24 1
PIN 1 INDICATOR *2.45 2.30 SQ 2.15
6
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
(BO OMVIEW) TT
13 12
7
0.23 MIN 2.50 REF
0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08
SEATING PLANE
0.30 0.23 0.18
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
080808-A
*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 EXCEPT FOR EXPOSED PAD DIMENSION
Figure 33. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad CP-24-2 Dimensions shown in millimeters
ORDERING GUIDE
Model ADCLK846BCPZ 1 ADCLK846BCPZ-REEL71 ADCLK846/PCBZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ Evaluation Board
Package Option CP-24-2 CP-24-2
Z = RoHS Compliant Part.
Rev. A | Page 15 of 16
ADCLK846 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07226-0-6/09(A)
Rev. A | Page 16 of 16

▲Up To Search▲

Price & Availability of ADCLK846

	To Download ADCLK846 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .